1. Field of the Invention
This invention generally relates to a non-volatile memory, and especially to a program method and circuit of non-volatile memory, which utilizes a constant charge type for programming storage state.
2. Description of Related Art
FIG. 1 is a drawing, schematically showing a view of a conventional AG-AND type memory. As shown in FIG. 1, when a current Id flows from a terminal Vd to a terminal Vs, an AG-AND memory 100 can conveniently injects and stores electrons into a floating gate (FG) of the memory 100 to accomplish the programming storage action of the memory. The most difference between the AG-AND memory 100 and a common transistor is that the gate electrode terminal comprises two control terminals which are the terminal WL and the terminal AG, so that when the current Id from the terminal Vd to the terminal Vs will be conducted by the AG-AND memory 100, the voltages of two terminals WL and AG must be controlled at same time in order to perform the programming action at this time.
In a common manufacture process of the AG-AND memory 100, the current channel in the each AG-AND memory is different which is caused by manufacturing process, it means that the length and the width of the current channel in each of the AG-AND memory 100 is different when accomplishing the manufacture, so that the stored electric charge amount is also different when the electrons are injected into the terminal FG through the current Id. For example, when the channel length of the AG-AND memory 100 is longer, the necessary time of injection must be longer, whereas, when the channel length of the AG-AND memory 100 is shorter, the necessary time of injection is relatively shorter. But, when the time of injecting the current Id is too short, it can be caused that amount of the electrons stored in the terminal FG is not enough, therefore the correctness of the programming result of the AG-AND memory 100 at this time is affected.
Further, excepting the above mentioned problem, an initial threshold voltage Vt of the each AG-AND memory 100 can also affect the injection time of the current Id. When critical voltage Vt of the each AG-AND memory 100 is higher, the current Id is lower, therefore the amount of the electrons injected into the terminal FG of the AG-AND memory 100 is lower. Whereas, when initial threshold voltage Vt is too low, the amount of the electrons injected into the terminal FG of the AG-AND memory 100 is relatively higher. In order to solve and improve the problem, the only way is to adjust the programming time of the current Id in the each AG-AND memory 100, but the problem solving method is very complex and can not be accomplished easily.
FIG. 2 is a drawing, schematically showing a circuit of a conventional array type AG-AND memory. As shown in FIG.2, the array type AG-AND memory includes four data lines 201 to 207, the each data line includes two set AG-AND memory components 211 and 213. All of the above mentioned data lines are coupled to the same voltage source 220, and by the voltage source 220 the current Id is supplied to each of the data lines 201 to 213. Further, the current amount supplied by the voltage source 220 can be even distributed to each of the data lines.
Supposing that the gross current amount supplied by the conventional voltage source 220 is 1.2 mA, then the maximum current Id supplied to each of the data lines is 0.3 mA, the current Id can perform the storage program of electrons to one set of the AG-AND memory components in each of the data lines thereof. But, when supposing that, owing to a short-cut accident, a set leakage current Ie is generated at the terminals Vd and Vs of the AG-AND memory component 213b in the data line 201, the data line not only must originally supply the current Id for the AG-AND memory component 211a, but also have to supply a additional current for the leakage current Ie, therefore, though originally the current amount 0.3 mA can be even distributed to each of the data lines, because that the leakage current Ie is generated, the current amount, which all of the AG-AND memory components can be obtained, is changed which can cause a mistake to the data storing in the memories in the whole array circuit, of course the serious mistake is not expected by circuit designers.